As a positioning system using positioning satellite signals, GPS (Global Positioning System) has been widely known and used for GPS receivers built in cellular phones, car navigation systems, etc. In GPS, location calculation of obtaining location coordinates and clock errors of a location calculation device is performed based on information of locations of a plurality of GPS satellites and pseudo distances from the respective GPS satellites to the GPS receiver.
The GPS satellite signals sent out from the GPS satellites are modulated using spread codes called C/A (Coarse and Acquisition) codes different from one GPS satellite to another. In order to acquire GPS satellite signals from weak received signals, the GPS receiver acquires GPS satellite signals by performing correlation calculation of the received signals and replica codes simulating the C/A codes.
For example, JP-A-2011-15159 has disclosed a correlation device that realizes correlation calculation of input signals and replica codes by arranging product-sum operators performing product-sum calculation of the input signals and the replica codes in parallel for product-sum calculation.
Recently, for realization of downsizing of electronic equipment containing the GPS receiver and prolonged driving using a battery, power saving of the GPS receiver has been required. In the GPS receiver, a correlation circuit has a higher operating rate and higher power consumption, and power saving of the correlation circuit has been desired.
Using the so-called deep submicron semiconductor technology, reduction of the power consumption using lower voltage and speeding up of the correlation calculation in the correlation circuit may be realized to some degree. However, the correlation circuit in related art is designed based on a synchronous design method and clock is essential, and there is a natural limit to reduction of the power consumption and speeding up of the calculation. For example, to realize speeding up of the calculation, it is necessary to raise the frequency of the clock for driving of the correlation circuit or parallelize the circuit, however, in this case, there is a problem that the power consumption increases in proportion to the frequency of the clock and the degree of the parallelization of the circuit.
Further, a full adder has been widely known as a calculator for addition of given input data. A full adder circuit including one-bit full adders connected in cascade arrangement is called ripple carry type and enables addition of data having arbitrary number of digits by connection of carry output from the lower digit to carry input of the higher digit (for example, JP-A-11-143684, JP-A-2004-265204).
The full adders for the number of digits of calculation are typically cascade-connected, and generally, the circuit size increases with increase of the number of digits. For example, in the case where a full adder circuit of cumulatively adding given input data is formed, full adders for the assumed number of digits as the final cumulative value are cascade-connected. However, as the number of digits of the final cumulative value is larger, the circuit size becomes larger. The increase of the circuit size leads to increase in power consumption and increase in cost, and is desirably suppressed as low as possible. Further, for example, in the case of a circuit having a higher operating rate and the smaller number of digits for one addition than the final cumulative value like the correlation circuit, requirement for reduction of the circuit size is stronger.
In addition, a circuit in related art including the full adder circuit is generally a synchronous type that operates in synchronization with a predetermined clock signal. The increase of the circuit size in the synchronous type also causes problems of larger current and clock skew of the clock signal. Moreover, above all, in the synchronous type, it may be impossible to speed up the circuit calculation to the higher speed than the clock frequency.
Furthermore, in related art, a circuit for detecting the maximum value from input data has been known. For example, JP-A-2004-73735 has disclosed a detection circuit for detecting the maximum value from input data. The maximum value detection circuit is to detect the maximum value in the input data by comparing magnitude between data supplied from an external system at each one clock and data stored in a register, and updating and storing data having the larger value in the register.
The detection circuit of the maximum value that has been known in related art is a synchronous detection circuit designed based on a synchronous design method. That is, a circuit block forming the detection circuit is designed to operate in synchronization with the clock signal.
However, in the synchronous circuit, there has been an issue that the problem of the larger current and clock skew of the clock signal occurs. Further, in addition, issues specific to the synchronous circuit that speeding up of the circuit operation to the higher speed than the clock frequency is not expectable and the power consumption of the entire circuit increases in proportion to the clock frequency are problematic.